Modeling and analysis of open defect in through silicon via (TSV) channel

Abstract

Vertical interconnections of stacked chips through the silicon substrates have enabled higher performance of electronic products with lower power consumption. The advantage of through silicon via (TSV) technique can be maximized by increasing the number of I/Os, which requires fine pitch and smaller diameter. The scale-down of TSVs results in decreased yield level caused by lack of precision in fabrication process. Among various types of possible defects, open defect creates a disconnection in the channel, electrically separating the transmitting terminal from the receiving target. In this paper, the equivalent circuit model for open defect is proposed and inserted as circuit component in a circuit model for defect-free channel. Open defect is analyzed in different locations along the channel to examine the effect in signal transmission characteristics.