A Higher Performance Accelerator for Resource-Limited FPGA to Deploy Deeper Object Detection Networks

Abstract

Nowdays, CNN models become more and more popular in lots of fields due to its high performance. Unfortuna-tely, the complexity of the model increases along with accuracy, which limited its applications in some fields. Until now, a lot of researches are focused on some shallow networks such as Alexnet, VGG16. The state of art models in computer vision has over one hundred layers using ResNet structure. Besides, the power consumption of the model and latency of inference also leads to the difficulties to use AI models in reality. To solve the problem, we proposed an accelerator structure to apply yolov5 model to FPGA boards. Two types of parallelisms and pipeline structure are applied. Besides, to eliminate the time of loading and saving to off-chip buffer, ping-pong buffer are used. We improve the pipeline performance by rescheduling the mac operation. Eventually, we test the performance of accelerator on ZC702. So it can be easily implemented on some resource-limited boards. The acc-elerator can speed up the inference 6 times than CPU, 17.4 times than ARM CPU on ZC702. And the throughput of single DSP outperforms the previous works.