High-Throughput RFIC Wafer Testing

Abstract

This paper surveys the state of RFIC wafer testing as performed on production floors today, and the trends and expectations for the future. Currently, most RF chips sold as known-good die (KGD) and relatively complex RFICs are tested at-speed at the wafer level. RF wafer testing is used to reduce the cost of scrap at the next level of packaging, and various test strategies are pursued to reduce test costs. The hardware options and tradeoffs for production testing are surveyed. Finally, the outlook for test cost, ATE resources, chip connection density, and for emerging technologies such as built-in self-test, are discussed.