HIGH FREQUENCY WAFER PROBING AND POWER SUPPLY RESONANCE EFFECTS

Abstract

The majority of wafer-level testing of digital devices is condiicted at frequencies below about 10 MHz. This is often ifhe case even when the IC is expected to operate at many times that rate in a system environment. To some extent, low frequency wafer probing can be supplemented by high frequency testing of the packaged device. However, the increased use of multi-chip packaging techniques makes at-speed wafer or die testing mandatory for many applications. Power supply decoupling is critical at fre

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高频晶圆探测和电源共振效应

大多数数字器件的晶圆级测试都以低于约10mhz的频率为条件。即使在系统环境中期望IC以该速率的许多倍运行，也经常会出现这种情况。在某种程度上，低频晶圆探测可以通过封装器件的高频测试来补充。然而，多芯片封装技术的使用增加使得高速晶圆或芯片测试在许多应用中是强制性的。电源去耦在大约SoMHz以上的频率下是至关重要的，适当的技术通常与频率有关。在本文中，我们回顾了在几百兆赫的频率范围内用于高针脚数器件(40至100或更多针脚)和多个千兆赫的频率范围内用于低至中等针脚数[1 - 0]的此类测试的选项。提出了一种预测高频晶圆探测噪声影响的电路模型。

本文章由计算机程序翻译，如有差异，请以英文原文为准。