Esteban A. Sanabria-Villalobos, L. Chavarría-Zamora, Leonardo Araya-Martinez
{"title":"A Novel Proposal for a Standalone Compressor and Decompressor Hardware Module from ISA","authors":"Esteban A. Sanabria-Villalobos, L. Chavarría-Zamora, Leonardo Araya-Martinez","doi":"10.1109/LAEDC54796.2022.9907767","DOIUrl":null,"url":null,"abstract":"Rapidly evolving markets and growing demand of digital application by consumers, along with hardware long time-to-market and rising manufacturing costs, are pushing the market towards software-based development, directly increasing power, area and memory requirements of current computer systems. Efforts to reduce this growing demand on storage devices are multiple, among them are assembly code compression and decompression techniques, which reduce the memory footprint of programs, thus reducing the resources and costs necessary for their elaboration. For this reason, is proposed a digital design and implementation of a real-time assembly code decompression module, that works under the demand of a processor, which is independent of the ISA, does not require modifications of the processing systems and reduce the amount of memory needed. The proposed microarchitecture is capable of decompress code in real-time, as well the results of the evaluation of the module, consisting of a 32-bit ARM processor and memory holding the compressed instructions, show the adaptability of the module to different ISA and processors using just their common inputs and outputs.","PeriodicalId":276855,"journal":{"name":"2022 IEEE Latin American Electron Devices Conference (LAEDC)","volume":"782 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE Latin American Electron Devices Conference (LAEDC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/LAEDC54796.2022.9907767","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
Rapidly evolving markets and growing demand of digital application by consumers, along with hardware long time-to-market and rising manufacturing costs, are pushing the market towards software-based development, directly increasing power, area and memory requirements of current computer systems. Efforts to reduce this growing demand on storage devices are multiple, among them are assembly code compression and decompression techniques, which reduce the memory footprint of programs, thus reducing the resources and costs necessary for their elaboration. For this reason, is proposed a digital design and implementation of a real-time assembly code decompression module, that works under the demand of a processor, which is independent of the ISA, does not require modifications of the processing systems and reduce the amount of memory needed. The proposed microarchitecture is capable of decompress code in real-time, as well the results of the evaluation of the module, consisting of a 32-bit ARM processor and memory holding the compressed instructions, show the adaptability of the module to different ISA and processors using just their common inputs and outputs.