Random Jitter Analysis and Measurement for Reference Clock Network in PCIe Gen3

Abstract

The Random Jitter (RJ) of the reference clock network to PCI express (PCIe) Gen3 was analyzed and compared with the measurement. The RJ was calculated using the phase noise results, which is analyzed from the on-chip clock network including Crystal (Xtal), IO pad, PCIe PHY to the SMA connectors of a test board, and the transfer function of PCIe Gen3 IP. The RJ was measured through the compliance test using an oscilloscope. The calculated RJ values show excellent agreement with the measured RJ values from the compliance test with -2.5% and 1.9% errors for two sample chips, respectively. As a result, if the proposed RJ analysis method is used, the RJ specification can be verified at the design stage through RJ analysis of the PCIe reference clock and a design can be made that minimizes system cost.