{"title":"Design and implementation of high-efficiency and low-power DC-DC converter with PWM/PFM modes","authors":"Jing Wang, Wenchao Gong, Lenian He","doi":"10.1109/ICASIC.2007.4415701","DOIUrl":null,"url":null,"abstract":"A high-efficiency low-power multimode DC-DC converter with pulse-width modulation (PWM) and pulse-frequency modulation (PFM) is proposed. This converter works in PWM mode on heavy load condition. In order to improve efficiency, it switches to PFM mode on light load condition. With suitable control and mode switch method, both simulation and chip test results indicate that the converter performs seamless switching between PWM and PFM modes. The total output voltage error, including line and load regulation, is less than plusmn2%, the maximum quiescent current is less than 15 muA, the maximum of efficiency reaches 92.6%. Simulated and implemented in CSMC 0.5 mum CMOS process.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"41 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 7th International Conference on ASIC","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICASIC.2007.4415701","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 7
Abstract
A high-efficiency low-power multimode DC-DC converter with pulse-width modulation (PWM) and pulse-frequency modulation (PFM) is proposed. This converter works in PWM mode on heavy load condition. In order to improve efficiency, it switches to PFM mode on light load condition. With suitable control and mode switch method, both simulation and chip test results indicate that the converter performs seamless switching between PWM and PFM modes. The total output voltage error, including line and load regulation, is less than plusmn2%, the maximum quiescent current is less than 15 muA, the maximum of efficiency reaches 92.6%. Simulated and implemented in CSMC 0.5 mum CMOS process.