Design of reconfigurable carry select adders

Jin-Fu Li, Yao-Chang Kuo, Chao-Da Huang, Tsu-Wei Tseng, C. Wey
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引用次数: 1

Abstract

Digital signal processing (DSP) processors for real-time processing of multimedia signals usually include fast reconfrgurable parallel adders for the operations of integers with different precisions. This paper presents a reconfrgurable carry select adder (CSA). High reconfrgurability is achieved with inter-block and intra-block partition schemes. This methodology only causes very small performance penalty and area overhead. Experimental results show that the worst delay ofa 64-bit reconfigurable CSA with eight 8-bit blocks is about 2.4ns based on the TSMC 0.18pm technology. Also, the area overhead ofthe additional partition circuitry is only about 4.6%.
可重构进位选择加法器的设计
用于实时处理多媒体信号的数字信号处理(DSP)处理器通常包括用于不同精度整数运算的快速可重构并行加法器。提出了一种可重构进位选择加法器(CSA)。通过块间和块内分区方案实现了高可重构性。这种方法只会造成很小的性能损失和面积开销。实验结果表明,基于TSMC 0.18pm技术的8位8位块的64位可重构CSA的最大延迟约为2.4ns。此外,额外分区电路的面积开销仅为约4.6%。
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