Jin-Fu Li, Yao-Chang Kuo, Chao-Da Huang, Tsu-Wei Tseng, C. Wey
{"title":"Design of reconfigurable carry select adders","authors":"Jin-Fu Li, Yao-Chang Kuo, Chao-Da Huang, Tsu-Wei Tseng, C. Wey","doi":"10.1109/APCCAS.2004.1413006","DOIUrl":null,"url":null,"abstract":"Digital signal processing (DSP) processors for real-time processing of multimedia signals usually include fast reconfrgurable parallel adders for the operations of integers with different precisions. This paper presents a reconfrgurable carry select adder (CSA). High reconfrgurability is achieved with inter-block and intra-block partition schemes. This methodology only causes very small performance penalty and area overhead. Experimental results show that the worst delay ofa 64-bit reconfigurable CSA with eight 8-bit blocks is about 2.4ns based on the TSMC 0.18pm technology. Also, the area overhead ofthe additional partition circuitry is only about 4.6%.","PeriodicalId":426683,"journal":{"name":"The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.","volume":"34 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/APCCAS.2004.1413006","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
Digital signal processing (DSP) processors for real-time processing of multimedia signals usually include fast reconfrgurable parallel adders for the operations of integers with different precisions. This paper presents a reconfrgurable carry select adder (CSA). High reconfrgurability is achieved with inter-block and intra-block partition schemes. This methodology only causes very small performance penalty and area overhead. Experimental results show that the worst delay ofa 64-bit reconfigurable CSA with eight 8-bit blocks is about 2.4ns based on the TSMC 0.18pm technology. Also, the area overhead ofthe additional partition circuitry is only about 4.6%.