Common Mode Voltage reduction in Diode Clamped MLI using Phase Disposition SPWM Technique

Abstract

The aim of this paper is to reduce the Common Mode Voltage (CMV) in the Diode Clamped Multilevel Inverter (DCMLI). Three phase star connected RL load is connected to DCMLI. The common mode voltage exists between star point of load & system ground. Premature failure of bearings of Induction Motor (IM) is caused by CMV and is necessary to reduce. In this paper, Phase Disposition Sinusoidal Pulse Width Modulation (PD SPWM) technique is used for reduction of CMV and LC filter is used for reduction of Harmonics. MATLAB Simulink is used for the simulation of circuit. Total Harmonic Distortion (THD) and CMV are investigated.