Reconfigurable low power MPEG-4 texture decoder IP design

Abstract

We propose a reconfigurable low-power MPEG-4 texture decoder IP design to support up to MPEG-4 SP@L3 video decoding. The proposed texture decoder IP includes an optimized DC/AC prediction and low-power adder-based inverse discrete cosine transform (IDCT) processor. In order to increase the flexibility, the proposed design can be reconfigured to decode MPEG-4 video with different frame sizes without modifying the architecture. For reducing the power consumption, we have re-arranged the MPEG-4 texture decoding flow, exploited efficient adder-based algorithm and DPGC-based architecture for IDCT processor, and adopted the zero vector detection technique in skipping the IDCT operations on zero data. The implementation results show that the proposed texture decoder IP design costs 11698 gates and 9472 bits memory for supporting the MPEG-4 CIF video texture decoding @ 30Hz under the TSMC 0.35/spl mu/m CMOS technology.