Reducing Search Space for Fault Diagnosis: A Probability-Based Scoring Approach

Abstract

Fault diagnosis is one of the most important phases in the VLSI design cycle. This paper proposes a probabilistic solution for the fault diagnosis in the sequential scan-based circuits. Our approach uses a signal probability analysis to score and rank potential fault locations. The ranking results are exploited to reduce the search space for exact diagnosis approaches. The experimental results show how this technique can increase the scalability and speed of satisfiability (SAT)-based diagnosis approach.