Statistical analysis of 6T SRAM data retention voltage under process variation

Abstract

One of the main issues in scaled SRAMs is the increase in static power. A common way to reduce the static power consumption of an SRAM array is to decrease its supply voltage when in memory retention mode. Decreasing the supply voltage however has a strong negative effect on the stability of the SRAM cell. This paper statistically analyzes the behavior of the 6T SRAM cell in data retention mode, under process variability. The failure probabilities under various supply voltages are determined for different technology nodes, and the Data Retention Voltage is determined. For the 45nm PTM SRAM cell under random threshold voltage variation, the Data Retention Voltage is found to be 423mV while for the 16nm PTM SRAM, the DRV is 649mV.