T. Tannert, M. Grözing, M. Berroth, C. Schmidt, J. Choi, C. Caspar, J. Schostak, V. Jungnickel, R. Freund, H. Rücker
{"title":"Analog 2:1 Multiplexer with over 110 GHz Bandwidth in SiGe BiCMOS Technology","authors":"T. Tannert, M. Grözing, M. Berroth, C. Schmidt, J. Choi, C. Caspar, J. Schostak, V. Jungnickel, R. Freund, H. Rücker","doi":"10.1109/BCICTS50416.2021.9682492","DOIUrl":null,"url":null,"abstract":"We report on a 2:1 analog multiplexer (AMUX) circuit in 130-nm SiGe BiCMOS technology. The technology offers HBTs with peak fT of 470 GHz and fmax of 650 GHz. S-parameter measurements of the AMUX IC show a significant leap in bandwidth compared to the circuit in the previous technology generation. The linear signal path offers a 3-dB-bandwith beyond 110 GHz, while the limiting clock path has 85 GHz 3-dB-bandwidth. With this circuit two digital-to-analog converters (DACs) can be time-interleaved, to generate multi-level signals far beyond 100 GBaud with both high bandwidth and linearity.","PeriodicalId":284660,"journal":{"name":"2021 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"134 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/BCICTS50416.2021.9682492","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 6
Abstract
We report on a 2:1 analog multiplexer (AMUX) circuit in 130-nm SiGe BiCMOS technology. The technology offers HBTs with peak fT of 470 GHz and fmax of 650 GHz. S-parameter measurements of the AMUX IC show a significant leap in bandwidth compared to the circuit in the previous technology generation. The linear signal path offers a 3-dB-bandwith beyond 110 GHz, while the limiting clock path has 85 GHz 3-dB-bandwidth. With this circuit two digital-to-analog converters (DACs) can be time-interleaved, to generate multi-level signals far beyond 100 GBaud with both high bandwidth and linearity.