Y. Takahashi, T. Ishii, H. Kanda, M. Arimura, M. Sugiyama, T. Tashiro, T. Shimizu
{"title":"\"A 1.6ns 64kb ECL RAM with 1K gate logic\"","authors":"Y. Takahashi, T. Ishii, H. Kanda, M. Arimura, M. Sugiyama, T. Tashiro, T. Shimizu","doi":"10.1109/VLSIC.1989.1037495","DOIUrl":null,"url":null,"abstract":"","PeriodicalId":136228,"journal":{"name":"Symposium 1989 on VLSI Circuits","volume":"35 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1989-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Symposium 1989 on VLSI Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.1989.1037495","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}