Fault detection and fault diagnosis techniques for lookup table FPGAs

Abstract

In this paper, we present a novel fault detection and fault diagnosis technique for field programmable gate arrays (FPGAs). The cell is configured to implement a bijective function to simplify the testing of the whole cell array. The whole chip is partitioned into disjoint one-dimensional arrays of cells. The input patterns can be easily generated with a k-bit binary counter. According to the characteristics of the bijective cell function, a novel built-in self-test structure is also proposed. To locate a faulty CLB (configurable logic block), two diagnosis sessions are required. However, the maximum number of configurations is k+4 for diagnosing a faulty CLB. The diagnosis complexity of our approach is also analyzed. Our results show that the time complexity is independent of the array size of the FPGA. In other words, we can make the FPGA array C-diagnosable with our approach.