Accelerated fault simulation utilizing multiple-fault propagation

Abstract

An efficient parallel pattern multiple-fault propagation (MFP) technique for the single stuck-at fault simulation in combinational circuits is presented. This technique is able to operate in conjunction with several existing fault simulation techniques, such as the parallel-pattern simulation and the fanout-free region concept. Experimental results have shown significant improvements in the simulation speed over the existing approaches. The fault simulator described adopts different simulation algorithms at different simulation stages to optimize the simulator performance.<>