InP HBT self-aligned technology for 40 Gbit/s ICs: fabrication and CAD geometric model

Abstract

InP/InGaAs DHBT technology for 40 Gb/s ICs is first presented. For these circuit applications, a sufficient breakdown voltage (>5 V), a static gain around 50, cutoff frequencies (f/sub T/) and maximum oscillation frequencies (f/sub max/) greater than 100 GHz are needed. High performance InP/InGaAs DHBT grown by chemical beam epitaxy (CBE) are reported with 125 GHz f/sub T/, 128 GHz f/sub max/ and a gain of 50 at a current density of 1/spl times/10/sup 5/ A/cm/sup 2/. Devices geometry optimisation is performed using a geometric model based on a set of analytical equations. This tool allows not only technological optimisation but also function-adapted individual sizing of the devices in the circuits.