Researchment and design of CMOS low noise amplifier in UHF band

Hua-qing Xiao, X. Xiong, C. Liao
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Abstract

To overcome difficulties among power, noise figure(NF) and match in the design of low-noise amplifier(LNA), a novel approach that can realize effective compromise among them is presented through analyzing the cascade LNA configuration. Under the premise that power can be accepted, the new approach can be achieved by adopting series inductors in input port, adding capacitors between gate and source nodes and appending series inductor-resistance to the output port. Experimental results show that, with the proposed approach, a 0.18 mum CMOS LNA at 2.4 GHz could provide a maximum NF of 0.46 dB, a minimum power gain of 22 dB in 3 dB bandwidth, input and output VSWRs which are better than 1.12, the output P1dB power of 1.07 dBm and 25.02 mW whole power consume. Theory analysis agrees well with the simulation results.
超高频CMOS低噪声放大器的研究与设计
针对低噪声放大器设计中功率、噪声系数和匹配之间的矛盾,通过对级联低噪声放大器结构的分析,提出了一种有效折衷低噪声放大器功率、噪声系数和匹配的方法。在功率可接受的前提下,通过在输入端采用串联电感,在栅极和源节点之间增加电容,在输出端附加串联电感电阻来实现新方法。实验结果表明,采用该方法,2.4 GHz 0.18 μ m CMOS LNA在3 dB带宽下的最大NF值为0.46 dB,最小功率增益为22 dB,输入输出VSWRs均优于1.12,输出P1dB功率为1.07 dBm,总功耗为25.02 mW。理论分析与仿真结果吻合较好。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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