3-D Multichip Packaging for Memory Modules

Abstract

High density memory packaging is important for high performance computing systems and for small size memory systems. Smaller single chip packages as well as multichip packages have been developed for these applications. Three-dimensional (3-D) packaging is another technique that provides size and performance benefits. Memory chips are well suited to 3-D stacking techniques due to the relatively low number of I/O terminals, the ability to share many common signal lines, and low power dissipation. This paper presents an analysis of recent worldwide developments in 3-D multichip packaging for memory modules, including analyses of assembly processes and vertical interconnection.