Performance modelling of heterogeneous ISA multicore architectures

2016 IEEE East-West Design & Test Symposium (EWDTS) Pub Date : 2016-10-01 DOI:10.1109/EWDTS.2016.7807641

N. Boran, Rameshwar Prasad Meghwal, Kuldeep Sharma, Binod Kumar, Virendra Singh

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引用次数: 3

Abstract

Recent research has shown that heterogeneous multicore architectures have the potential to further improve single thread performance. In such architectures different phases of the application are executed on different cores to improve performance and energy efficiency. However, restricting the cores to a single ISA limits the achievable performance gain. Different phases of applications also have shown affinity towards different ISAs due to their characteristics, functionality etc. Heterogeneous ISA architectures thus attempt to execute these different phases on their respective affine cores to fully harness ISA diversity. However, in such architectures, estimating the best migration point from one ISA to another, is an open research problem. This paper proposes a performance model for execution time estimation of heterogeneous ISAs which naturally extends to dynamic scheduling. The model is centred around execution time and a few on-line parameters. Regression techniques have been used to model the performance. Experimental evaluation shows that the proposed model has 78% accuracy in estimating migration from ARM ISA to X86 ISA.

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异构ISA多核架构的性能建模

最近的研究表明，异构多核架构具有进一步提高单线程性能的潜力。在这样的体系结构中，应用程序的不同阶段在不同的核心上执行，以提高性能和能源效率。然而，将核心限制为单个ISA限制了可实现的性能增益。应用程序的不同阶段也因其特性、功能等而对不同的isa表现出亲和力。因此，异构ISA架构试图在各自的仿射核心上执行这些不同的阶段，以充分利用ISA的多样性。然而，在这样的体系结构中，估计从一个ISA到另一个ISA的最佳迁移点是一个开放的研究问题。本文提出了一种异构isa执行时间估计的性能模型，并将其自然地扩展到动态调度。该模型以执行时间和几个在线参数为中心。已使用回归技术对性能进行建模。实验结果表明，该模型对ARM ISA向X86 ISA迁移的估计准确率为78%。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2016 IEEE East-West Design & Test Symposium (EWDTS)

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