Timing simulation with VHDL simulators

Abstract

We propose an original method for timing simulation within a VHDL logic simulator framework. This method enables standard VHDL simulator to evaluate the longest path delays to all the signals in the circuit with only one run of the logic simulator. Timing simulation is performed at simulation time t=0 at the cost of a negligible increase of CPU time needed for the simulation. Results of the timing simulation of the ISCAS'85 benchmark circuits with a VHDL simulator are presented that prove that the proposed method is extremely efficient and appropriate for interactive use in the early phases of the design process where timing analysis needs to be repeated as the circuit design is optimized or refined.