Digital post-correction on dynamic nonlinearity in GaN HEMT track-and-hold sampling circuits

Abstract

This paper introduces the recent development of GaN HEMT track-and-hold sampling circuits (THSCs) with a digital post-correction (DPC) technique for emerging applications. Compared to THSCs in silicon technologies, GaN THSCs achieve 20–30 dB higher signal-to-noise ratio (SNR) for a given bandwidth. Nevertheless, GaN THSCs suffer from dynamic nonlinearity due to charge trapping and introduce low-frequency dispersion, thus providing no more than 40–50 dB spurious-free dynamic range (SFDR). Conventional DPC techniques have been used to linearize CMOS data converters with weak memory effects, which is not effective for dynamic nonlinearity correction on GaN HEMT THSCs with deep memory effects. In order to provide dynamic nonlinearity correction on GaN HEMT THSCs for Nyquist bandwidth, the proposed DPC technique based on a truncated Volterra series eliminates DC offset before model parameter extraction and also uses a multi-section input signal for wideband model training. The DPC technique is applied to a 200-MS/s 98-dB SNR GaN THSC with 56.7-dB SFDR for a 12-MHz input and 48.4-dB SFDR for a 98-MHz input. After DPC, the SFDR improves to 77.9 dB at 12 MHz and 82.2 dB at 98 MHz, demonstrating 21.2 dB and 33.8 dB improvement respectively. The GaN THSC with DPC achieves 12.4-bit ENOB with a 98-MHz input, higher than prior CMOS sampling circuits reported to date.