The Architecture Of Wafer Scale Memories With Giant Magneto-resistance Memory Cells

Abstract

For practical wafer scale memories to be achieved, the memory cells in the structure must have a number of properties. First the memory cells must be non-volatile so that unloading on shut down and loading on start up are not necessary. Secondly, it should be possible to power up the cells in a short time and shut them off quickly so that only a small fraction of the wafer is powered at one time. The cells should have infinite write and read capability with cycle times of at most a few microseconds. It must be possible to make small sub-sections of the wafer with high yield with provisions to discard malfunctioning sub-sections. Simple bus structures must be possible to supply power and carry addresses and signals. The cells should be simple to make with few masking steps and have a high density set by minimum metal pitch for two layers of metal (1). To provide economical packaging, the memory cells should integrate with the semiconductor drive electronics.