Three-level decomposition with application to PLDs

[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI:10.1109/ICCD.1991.139989

A. A. Malik, D. Harrison, R. Brayton

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引用次数: 30

Abstract

A scheme for programmable logic array (PLA) decomposition that consists of one level of PLAs followed by a second level of simple two-input logic gates is presented. The propagation delay is therefore the sum of the delay through one level of PLA and one level of two-input gates. Since the delay through a two-input gate is significantly less than that through a PLA, the timing performance of the new scheme is generally superior to those of earlier PLA decomposition schemes. The sizes of the PLAs used depend on the choice of the two-input gates. An algorithm is presented that chooses the functionality of the gates such that the areas of the first-level PLAs are minimized, further improving performance. The new decomposition scheme was developed for the automatic programming of a programmable logic device (PLD) which had basically a three level architecture. The functional unit for such a PLD is described and the application of the algorithm to the programming of these functional units is discussed. Experimental results show that the new scheme significantly reduces the area over the single PLA implementation.<>

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三层分解及其在pld中的应用

提出了一种可编程逻辑阵列(PLA)分解方案，该方案由一级PLA和二级简单双输入逻辑门组成。因此，传播延迟是通过一级PLA和一级双输入门的延迟之和。由于通过双输入门的延迟明显小于通过PLA的延迟，因此新方案的时序性能通常优于先前的PLA分解方案。使用的pla的大小取决于双输入门的选择。提出了一种选择门的功能的算法，使一级pla的面积最小化，进一步提高了性能。针对具有三层结构的可编程逻辑器件(PLD)的自动编程，提出了一种新的分解方案。描述了这种可编程逻辑器件的功能单元，并讨论了该算法在这些功能单元的编程中的应用。实验结果表明，与单PLA实现相比，新方案显著减小了面积

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors

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