Jianqiang Lin, L. Czornomaz, N. Daix, D. Antoniadis, J. D. del Alamo
{"title":"Ultra-thin-body self-aligned InGaAs MOSFETs on insulator (III-V-O-I) by a tight-pitch process","authors":"Jianqiang Lin, L. Czornomaz, N. Daix, D. Antoniadis, J. D. del Alamo","doi":"10.1109/DRC.2014.6872375","DOIUrl":null,"url":null,"abstract":"We report a self-aligned InGaAs Quantum-Well MOSFET (QW-MOSFET) on III-V-O-I substrate fabricated through a tight-pitch process. The ultra-thin body (UTB) III-V-O-I layer structure was fabricated on Si through a direct bonding technique. The III-V MOSFETs, with a self-aligned gate and metal contacts, were fabricated by a gate-last method. For the first time, we demonstrate adjacent devices with contact metal spacing of 150 nm. The fabrication features CMOS compatibility with a wet-etch free, lift-off free and Au-free process in the front end. Transport and short-channel effects (SCE) are studied as a function of back bias. Excellent SCE control is obtained with DIBL and subthreshold swing benchmarked against state-of-the-art III-V-O-I data. The reported technology provides a new path to integrate III-V front-end devices for future high density circuit applications.","PeriodicalId":293780,"journal":{"name":"72nd Device Research Conference","volume":"14 1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"72nd Device Research Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DRC.2014.6872375","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
Abstract
We report a self-aligned InGaAs Quantum-Well MOSFET (QW-MOSFET) on III-V-O-I substrate fabricated through a tight-pitch process. The ultra-thin body (UTB) III-V-O-I layer structure was fabricated on Si through a direct bonding technique. The III-V MOSFETs, with a self-aligned gate and metal contacts, were fabricated by a gate-last method. For the first time, we demonstrate adjacent devices with contact metal spacing of 150 nm. The fabrication features CMOS compatibility with a wet-etch free, lift-off free and Au-free process in the front end. Transport and short-channel effects (SCE) are studied as a function of back bias. Excellent SCE control is obtained with DIBL and subthreshold swing benchmarked against state-of-the-art III-V-O-I data. The reported technology provides a new path to integrate III-V front-end devices for future high density circuit applications.