A Comparative Study of Pulse Triggered Flipflops

Abstract

In this paper, we have compared and analyzed two architectures of implicit pulsed triggered flip-flop (P-FF). The Predictive Technology Model (PTM) 45nm and 32nm technology nodes are used for simulations. The variation in delay and power for both architectures with respect to variation in supply voltage (VDD) and temperature is analyzed. Results from simulations at 45nm show that design with conditional pulse-enhancement technique (CPE) is better in terms of power consumption whereas design using gated-pull up control (GPC) is less prone to temperature and supply voltage variation. Similar trends have been noticed at a 32nm technology node.