GPU Approach to FPGA placement based on star+

Abstract

While simulated-annealing is currently the most widely used method for performing FPGA placement, it does not scale to very large designs. Modern many-core architectures (including GPUs) offer a promising alternative to traditional multi-core processors for improving runtime performance. In this work, we propose a GPU-accelerated simulated-annealing variant for FPGA placement. Our approach uses the Star+ wirelength model along with a novel method of efficiently generating large sets of independent swap operations, providing a high level of parallelism. Speedups from 5.4-89.2× (median 20.2×) were achieved over a single-core CPU-only implementation.