A Low-Cost and High Performance Pipelined Code Decompression Engine for ARM-Series Processors

Abstract

Several techniques have been presented in our previous work for lessening the delays for instruction decompression when branching occurs. However, their costs are still relatively high. In this paper, a new preprocessing-based technique is presented to reduce the cost and increase the performance. The synthesized results for several benchmarks show that the average saving of area is about 37.5%.