Resistor-less power-rail ESD clamp circuit with ultra-low leakage current in 65nm CMOS process

Abstract

A resistor-less power-rail ESD clamp circuit realized with only thin gate oxide devices, and with SCR as main ESD clamp device, has been proposed and verified in a 65nm 1V CMOS process. Skillfully utilizing the gate leakage currents to realize the equivalent resistors in the ESD-transient detection circuit, the RC-based ESD-transient detection mechanism can be achieved without using an actual resistor to reduce the layout area in I/O cells. From the measured results, the proposed power-rail ESD clamp circuit with SCR width of 45μm can achieve 5kV HBM and 400V MM ESD levels under the ESD stress event, while consuming only a standby leakage current of 1.43nA at 25°C under the normal circuit operating condition with 1V bias.