FPGA Validation of Event-Driven ADPLL

Abstract

In this paper, we perform FPGA modeling of an event-driven all-digital phase locked loop (ADPLL) with asynchronous control. We perform the comparison with a theoretical model through a transient response, phase plane representation, and the order parameter. The hardware simulations showed a very good agreement with the theoretical model, which can be used for studying more complex ADPLL networks.