The Future of CMOS: More Moore or a New Disruptive Technology?

Nazek El‐atab, M. Hussain
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引用次数: 2

Abstract

For more than four decades, Moore’s law has been driving the semiconductor industry where the number of transistors per chip roughly doubles every 18–24 months at a constant cost. Transistors have been relentlessly evolving from the first Ge transistor invented at Bell Labs in 1947 to planar Si metal-oxide semiconductor field-effect transistor (MOSFET), then to strained SiGe source/drain (S/D) in the 90and 65-nm technology nodes and high-κ/metal gate stack introduced at the 45and 32-nm nodes, then to the current 3D transistors (Fin field-effect transistors (FinFETs)) introduced at the 22-nm node in 2011 (Figure 1.1). In extremely scaled transistors, the parasitic and contact resistances greatly deteriorate the drive current and degrade the circuit speed. Thus, miniaturization of devices so far has been possible due to changes in dielectric, S/D, and contacts materials/processes, and innovations in lithography processes, in addition to changes in the device architecture [1, 2]. The gate length of current transistors has been scaled down to 14 nm and below, with over 109 transistors in state-of-the-art microprocessors. Yet, the clock speed is limited to 3–4 GHz due to thermal constraints, and further scaling down the device dimensions is becoming extremely difficult due to lithography challenges. In addition, further scaling down the complementary metal-oxide semiconductor (CMOS) technology is leading to larger interconnect delay and higher power density [3]. The complexity of physical design is also increasing with higher density of devices. So, what is next? A promising More-than-Moore technology is the 3D integrated circuits (ICs) which can improve the performance and reduce the intra-core wire length, and thereby enable high transfer bandwidth with reduced latencies and power consumption, while maintaining compact packing densities [4]. Alternative technologies that could be promising for new hardware accelerators include resistive computing, neuromorphic computing, and quantum computing. Resistive computing could lead to non–von Neumann (VN) computing and enforce reconfigurable and data-centric paradigms due to its massive parallelism and low power consumption [5]. Moreover, humans can easily outperform current high-performance computers in tasks like auditory and pattern recognition
CMOS的未来:更多摩尔还是新的颠覆性技术?
四十多年来,摩尔定律一直推动着半导体行业的发展,在不变的成本下,每个芯片上的晶体管数量大约每18-24个月翻一番。从1947年贝尔实验室发明的第一个Ge晶体管到平面Si金属氧化物半导体场效应晶体管(MOSFET),再到90和65纳米技术节点的应变SiGe源/漏极(S/D),以及45和32纳米节点引入的高κ/金属栅极堆栈,再到2011年在22纳米节点引入的当前3D晶体管(Fin场效应晶体管(finfet)),晶体管一直在不断发展(图1.1)。在极窄的晶体管中,寄生电阻和接触电阻大大降低了驱动电流,降低了电路速度。因此,到目前为止,由于介质、S/D和触点材料/工艺的变化,以及光刻工艺的创新,以及器件架构的变化,器件的小型化已经成为可能[1,2]。目前晶体管的栅极长度已经缩小到14纳米以下,在最先进的微处理器中有超过109个晶体管。然而,由于热限制,时钟速度被限制在3-4 GHz,并且由于光刻技术的挑战,进一步缩小器件尺寸变得极其困难。此外,进一步缩小互补金属氧化物半导体(CMOS)技术将导致更大的互连延迟和更高的功率密度[3]。物理设计的复杂性也随着设备密度的增加而增加。那么,下一步是什么?3D集成电路(ic)是一种比摩尔技术更有前途的技术,它可以提高性能并减少芯内线长度,从而实现高传输带宽,降低延迟和功耗,同时保持紧凑的封装密度[4]。对于新的硬件加速器来说,有希望的替代技术包括电阻计算、神经形态计算和量子计算。电阻式计算可能导致非冯·诺伊曼(VN)计算,并由于其大规模并行性和低功耗而强制可重构和以数据为中心的范式[5]。此外,在听觉和模式识别等任务上,人类可以轻松超越目前的高性能计算机
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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