Investigating the Linearity Behavior of Dual Gate Junction less MOSFET with high-K Gate Stack at Cryogenic Temperatures

Abstract

This paper presents the linearity behavior of Dual Gate Junction less (JLDG) MOSFET with high-k gate stack down to cryogenic temperature (50K). Based on ATLAS device simulation data, the device characterization is demonstrated under cryogenic conditions in terms of surface potential, electron current density and output drain current. The impact of temperature is further studied over linearity parameters of the device e.g., transconductance (gm), higher order transconductance (gm3), third-order current intercept point (IIP3), third-order intermodulation distortions (IMD3), and higher-order voltage intercept point (VIP3). Such analysis will confirm the ability of the device to operate under cryogenic conditions for efficient quantum-computing applications.