Mobility extraction in sub 10nm nanowire nMOSFETs with gadolinium-silicate as gate dielectric

Abstract

Gadolinium-silicate (GdSiO) as high-k dielectric in sub 10nm gate first nanowire (NW) nMOSFETs is investigated. NW- and UTB- nMOSFETs with conventional SiO2/Poly-Si gate stacks have been fabricated and compared with GdSiO/TiN NW nMOSFETs. Specific nMOSFETs with multiple NWs in parallel have been used to extract the effective mobility by split-CV method and to eliminate the series resistance to correct the measured data.