An Efficient Hardware Implementation of Artificial Neural Network based on Stochastic Computing

Abstract

Recently, Artificial Neural Network (ANN) has emerged as the main driving force behind the rapid developments of many applications. Although ANN provides high computing capabilities, its prohibitive computational complexity, together with the large area footprints of ANN hardware implementations, has made it unsuitable for embedded applications with real-time constraints. Stochastic Computing (SC), an unconventional computing technique which could offer low-power and area-efficient hardware implementations, has shown promising results when applied to ANN hardware circuits. In this paper, efficient hardware implementations of ANN with conventional binary radix computation and SC technique are proposed. The system’s performance is benchmarked with a handwritten digit recognition application. Simulation results show that, on the MNIST dataset, the 10-bit binary implementation of the system only incurs an accuracy loss of 0.44% compared to the software simulations. The preliminary simulation results of the SC neuron block show that the output is comparable to the binary radix results. FPGA implementation of the SC neuron block has shown a reduction of 67% in the number of LUTs slice.