FPGA Implementation of Phase Disposition PWM (PD-PWM) Strategy for Cascaded H-Bridge Multilevel Inverter (CHB-MLI)

Abstract

Field-programmable gate array (FPGA)-based multi-carrier pulse-width modulation (MCPWM) generation technique is desirable for high-frequency dc/ac converter application where a fast-switching response is the primary concern. This paper offers an FPGA-based high-frequency, multi-carrier phase disposition pulse-width modulation (PDPWM) generation strategy that can support the requirements of modern fast-switching semiconductors. The FPGA architecture employs several pre-formulated VHDL-coded algorithms to develop a set of high-speed PD-PWM gating signals for the multilevel dc/ac converter. The proposed technique is verified through a Xilinx Spartan-6 FPGA-triggered cascaded H-bridge multilevel inverter (CHB-MLI) to quantify its merits among all the recently-reported similar architectures under study.