Reducing BIST hardware by test schedule optimization

Abstract

VLSI circuits are segmented using built-in self-test registers. During the test execution a signature is collected for each of the subcircuits. The author presents a set of test scheduling algorithms that minimize the hardware overhead required for test control and test evaluation under different restrictions. The subcircuit tests are ordered such that only a subset of the signatures must be scanned and evaluated at the end of the test. The algorithms allow a tradeoff between test time and test hardware overhead.<>