A 256 K dynamic RAM

Abstract

IN A CONTINUING EFFORT to lower the cost, and increase the density, a 256K x l b single transistor cell RAM has been designed, and assembled in a standard 300mil16pin DIP. The RAM is organized to be compatible with existing 16pin 16K RAMS and 16pin 64K RAMS. The pin configuration and the photo are shown in Figure 1. The chip is arranged as a 256 rows x 1.024 columns matrix and is organized internally as two 128K RAMS. The location of important circuit blocks on the chip is shown in Figure 2. The memory cell layout is shown in Figure 3. The cell measures 5.7 x 12.5pm and has a storage capacitance of 0.035pF by decreasing the cell capacitor oxide thickness to 200A. To reduce the ratio of digit line to cell capacitance, the digit line is formed in the second polysilicon layer. The resulting capacitance ratio is 20: 1. To reduce dynamic noise on the digit line caused by the substrate current ransients, the digit lines arc sheltered by the first polysilicon ground plane.