Coverage fulfillment methods as key points in functional verification of integrated circuits

Abstract

Considering progress in semiconductor manufacturing processes (where technology advanced creating transistors from 10 μm in 1971 to a few nm nowadays), integrated circuits have become more and more complex and have embedded huge number of functionalities. Consequently, functional verification of verification circuits designs highly increased in difficulty. Both the academic community and the industry are involved in research projects for obtaining an efficient thorough verification of circuit designs. Thoroughness of verification is defined by metrics fulfillment in verification process. Aligning to this global effort, in this paper, four methodologies of fulfilling coverage (most important component of metrics) are described and compared. The study is concerned on outcome of each method, and on implementation effort, as well.