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A Monolithic 622Mb/s Clock Extraction Data Retiming Circuit

1991 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1991-02-13 DOI:10.1109/ISSCC.1991.689102
B. Lai, R. Walker
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引用次数: 54
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一个单片622Mb/s时钟提取数据重定时电路
本文章由计算机程序翻译，如有差异，请以英文原文为准。
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1991 IEEE International Solid-State Circuits Conference. Digest of Technical Papers
1991 IEEE International Solid-State Circuits Conference. Digest of Technical Papers
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