Control of hot carrier degradation in LDMOS devices by a dummy gate field plate: experimental demonstration

Abstract

It is experimentally demonstrated that hot carrier degradation in high voltage LDMOS devices can be minimized by adding a dummy gate field plate, DGFP, over the drain drift region close to the gate. The level of on resistance increase due to hot carrier stress can be controlled by design with the amount of the DGFP overlap of the drift region. Significant decrease in the degradation is experimentally observed by a 40% DGFP overlap without substantially affecting the breakdown voltage of the device. It was also demonstrated that the initial peak substrate/body current is a good indicator of the hot carrier degradation effect and can be used as a process monitor.