USING BOUNDARY SCAN DESCRIPTION LANGUAGE IN DESIGN

Abstract

Starting with a VHDL description of a chip without IEEE 1149.1 Boundary Scan, the computer program described here creates a structural VHDL design for the boundary scan circuitry, using pre-defined boundary scan cells, pin driverlreceivers, and TAP Controller. One output file from the program is the Boundary Scan Description Language (BSDL) for the chip. Changes may be made to the boundary scan circuitry by manually editing the BSDL and rerunning the program with BSDL as an input file. Controller