Die-to-package coupling extraction for fan-out wafer-level-packaging

Abstract

In fan-out wafer-level-packaging, the package interconnection layers are fabricated similar to the back-end-of-line interconnect stack where multiple dies are tightly integrated with dense package routing for higher performance and lower power. However, electrical and magnetic field interactions may introduce significant uncertainties in system power and performance. For the first time, we provide two CAD flows for extracting coupling capacitance between the die and package. In particular, we first analyse the E-field interactions using field solvers and demonstrate their impacts on die-to-package coupling. We then propose a holistic extraction flow which integrates all layers from the chip and package and extracts all coupling elements for the maximum accuracy. We also propose an in-context extraction flow for chip designers, which only includes necessary regions of the redistribution layer and still captures the E-field impact from the package. Our in-context extraction requires less computing resources, allows heterogeneous integration, and is still highly accurate compared with the holistic extraction. Final, we demonstrate our flow using detailed package and multi-chip layout.