Test structures to evaluate the impact of parasitic edge FET on circuits operating in weak inversion

Abstract

Precision analog circuit accuracy in a microcontroller product was impacted by unmodeled behavior across the temperature range. Three critical analog circuits from the microcontroller were built and tested in discrete parametric test structures. It was shown that a process with reduced parasitic edge FET leakage dramatically improved the accuracy of the analog circuits, which were operating in the subthreshold region.