A bit-serial VLSI architecture for the 2-D discrete cosine transform

Abstract

In this paper, a VLSI architecture for the computation of the 2-D N × N-point Discrete Cosine Transform (DCT) is presented, where N is a power of 2. The proposed bit-serial architecture has highly regular structure and exhibits high data throughput rate. It is based on a high performance application specific multiplier. A chip was designed for the computation of the 4 × 4-point DCT exhibiting a performance of 246 Mpixels/sec.