Novel AI based pre-silicon Performance estimation and validation of complex System-on-Chip

Abstract

With the advancement of Very Large Scale Integration (VLSI) technology, the demand for integrating heterogeneous components (multi-core, graphics, high-bandwidth peripherals etc.) is increasing exponentially which is leading to the complex System-on-Chip (SOC) design. In this paradigm, the performance of complex SOC is the key matrix that defines various product portfolios across laptops, desktops, and servers market segments. The overall SOC performance depends on the numerous design and architectural parameters(frequency, cores, etc.) of the heterogeneous components integrated into the design. This leads to the necessity for performance estimation based validation of the SOC under different design and configuration parameters. Existing traditional standard methods incorporate time-consuming and non-exhaustive cycle-level simulations, which are slow and lead to incompleteness in achieving performance targets at pre-silicon level. The proposed novel AI based performance estimation based technique is used to obtain fast and accurate performance estimates for a complex SOC, which explores the design under multiple configurations without running simulation test content and aids in evaluating design Hardware (HW) bottlenecks and enhancing debug capabilities.