A Low Energy Two-Step Successive Approximation Algorithm for ADC Design

Abstract

This paper proposes a new method for switching the capacitors in the DAC capacitor array of a successive approximation register (SAR) ADC. By separating the decoding of the most significant bits and the least significant bits, and using two different capacitor arrays with unequal size to determine their values, respectively, the average switching energy of the capacitor arrays can be dramatically reduced compared to the conventional switching methods. The analysis of the switching energy reduction is presented. Experiments were carried out on a 10-bit SAR-ADC designed using a 0.35 mum CMOS process. HSPICE simulations show that significant reduction in energy consumption is achieved using the proposed design.