Hot carrier stress in 70-nm nMOSFET with various bias conditions

Abstract

This study presents a 70-nm nMOSFET degradation by hot carrier stress. The DC performance drifts of the device due to hot carrier stress are examined experimentally before and after stress for a 70-nm nMOSFET. Although the substrate current of a 70-nm nMOSFET has different characteristics from that of a long channel device, it can be a good indicator of hot carrier stress. The industrial practice to estimate the device lifetime using the measured lifetime versus 1/VDS plot cannot be applied to a 70-nm nMOSFET, but the method using the substrate current is useful to for this application.