Ternary Versus Binary Multiplication with Current-Mode CNTFET-Based K-Valued Converters

Abstract

In multiplication, partial products must first be generated by single-digit multipliers. Then, a parallel addition technique is required to add them. Both steps are addressed in this paper by proposing novel current-mode circuits in ternary logic. All of the designs are simulated by HSPICE and 32nm CNTFET. Moreover, the second step of multiplication is completely demonstrated in this paper for multiplying two five-digit ternary numbers. The method is based on the ability of linear addition in current-mode logic and redundant number sets. The ternary model is compared with a comparable binary structure. The findings of this paper show that the proposed ternary multiplier has 629 fewer transistors, and it also operates approximately 40% faster than the binary counterpart.