A 1448-Mpixel/s, 84-pJ/Pixel Display Stream Compression Encoder in 28 nm for 4K Video Resolution

Abstract

In this work, an energy- and area-efficient Display Stream Compression (DSC) encoder architecture is proposed for energy-constrained systems driving high-resolution internal/external display (e.g., virtual reality headsets, smartphones). As main motivation, relentlessly higher resolutions in video displays (e.g., 4K, 8K) require very high uncompressed processor-display data rates of 30 Gbps for 4K (120 Gbps for 8K) at 120 frames per second (fps) and 10 bits per component (bpc). The data transfer bandwidth to the display cannot keep pace with such demand, making compression a necessity.