Multilevel interconnect-driven floorplanner

Abstract

As technology continues to scale down, the number of transistors on a chip has increased rapidly and interconnect delay has become a dominant factor of system performance. Scalability and routability are two major concerns in floorplanning. In this paper, we present a multilevel floorplanner that addresses these important issues: congestion estimation, buffer planning and scalability. Experimental results show that this integrated multilevel approach, not only can handle large size problems, but can also improve the routability of the solution significantly by considering the interconnect issues.